Multi-objective Optimization of Mcml Circuits Using a Genetic Algorithm
نویسندگان
چکیده
This paper introduces the Pareto front as a useful analysis tool to explore the design space of MOS Current Mode Logic (MCML) circuits. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. As an example of the flexibility of this design automation approach, the results for an optimized fundamental inverter logic gate are presented. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task.
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